The ADC card (see fig.) is a 6-layer PCB 110mm by 260mm in size,1.6mm thick with 35µ copper plating on all layers. The layer assignment are shown in figure which depicts schematically the construction of the ADC Card. The PCB is designed with a small 12mil track-width and 12mil track-to-track spacing design rule. The via size used is 36mil. Two right-angled PCB mount SMA connectors couple the analog inputs to the PCB. A single 64-pin EURO connector is used for the backpanel. The analog and digital sections of the PCB are isolated from each other to ensure separate power-ground planes for the analog and digital sections. The two sections are coupled only at the ADC power-supply input pins.
The backpanel is 3.2mm, 6 layer PCB. Its construction is shown in figure. Each ADC card is an independent unit and there are no buses running on the backpanel which interconnect the ADC cards. Two Berg pins are provided with every ADC card for the ECL clock connections. The connections are wire-wrapped on the pins from a clock distribution card which is mounted adjacent to the backpanel in the rack.
A total of 60 cards are required for the entire system. Each backpanel supports 12 cards, with inner-card spacing of 7T(=1.4 inch). Thus a total of 5 sub-racks make up for the entire requirement. A total of 2 24U racks are used for the ADC system. One rack houses all the 5 sub-racks with fan-trays for forced cooling with the other rack houses the power supplies required by the 5 sub-racks. A schematic front view is shown in figure. The arrangement of the two racks is also shown in the following figure.
The interconnection of the ADC with the baseband system is accomplished by the 120 RG-223 coaxial cables. These cables have a TNC cable connector at the baseband end and a SMA cable connector at the ADC end. The digitised data is transmitted to the Delay subsystem via 120 14-core round twist-end-flat jacketed shielded cable. A OEN 7-by-2 IDC Cable connector assembly is used at both, the ADC as well as the Delay end.